The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a cylindrical capacitor.
In dynamic random access memories (DRAMs), the design rule has been shifted to miniaturization. Accordingly, the size of cells has also been scaled down. As a result, the height of cylindrical capacitors has increased. In order to obtain a sufficient level of capacitance, the thickness of dielectric layers of capacitors has to be decreased. This development trend is due to the fact that the capacitance of a capacitor is directly proportional to the area of electrodes and the dielectric constant of a dielectric layer of the capacitor, and inversely proportional to the distance between the electrodes (i.e., the thickness of the dielectric layer).
However, the increase in height of cylindrical capacitors induces difficulties in applying subsequent processes, and comprises many limitations. Thus, researchers are actively studying for various methods to decrease the thickness of the dielectric layer. In addition, researchers are also focusing on developing new electrode materials, for instance, a metal-based material, to replace polysilicon. When polysilicon is used as an electrode material, the decrease of the thickness of the dielectric layer may be limited due to the presence of an oxide layer formed on the electrode.
If a metal-based material is used as an electrode material, a crystal development, which is one characteristic of metals, appears. For instance, in the case of titanium nitride (TiN), crystals are grown to a columnar structure. Due to this crystal structure, the surface of TiN generally becomes rough, and a wet etch solution is likely to penetrate into a TiN-based electrode through interfaces between crystallines or a defective layer. Thus, when an oxide layer for molding a capacitor is removed by wet etching to form a cylindrical TiN-based bottom electrode, a bottom structure underneath the TiN-based bottom electrode is often damaged by the wet etch solution. As a result, operational malfunction or dysfunction in DRAMs may occur. Furthermore, the miniaturization is likely to cause formation of bridges between bottom electrodes during a dip-out treatment, which is one type of wet etching for removing an oxide layer.
FIG. 1A illustrates a sectional view of a conventional capacitor structure prior to a dip-out treatment. This sectional view is obtained when the capacitor structure is cut in X-X′ and Y-Y′ directions as illustrated in FIG. 1B. Particularly, stack structures, each including a storage node contact plug 13 and a barrier metal layer 14, both passing through a storage node contact oxide layer 12, are formed on a substrate 11. An etch stop layer 15 and a capacitor molding oxide layer 16 are formed on storage node contact oxide layer 12.
Capacitor molding oxide layer 16 and etch stop layer 15 are etched to form openings, and cylindrical storage nodes 17 are formed inside the openings. Capacitor molding oxide layer 16 is removed by a wet dip-out treatment to expose the inner and outer walls of storage nodes 17, so as to form a cylinder structure.
However, the miniaturization often causes cylindrical storage nodes 17 to be spaced closer to each other. Thus, even though the wet dip-out treatment is optimized, bridges are likely to form between cylindrical storage nodes 17.
FIG. 1B illustrates an image of conventional storage nodes 17 obtained after the wet dip-out treatment. Particularly, storage nodes 17 illustrated in FIG. 1B are likely to be bridged together due to decreased spacing distances between storage nodes 17. The spacing distances between storage nodes 17 in X-X′ direction is narrower than that in Y-Y′ direction. As a result, when the wet dip-out treatment is carried out, storage nodes 17 may not be supported firmly, resulting in collapsed and further bridged storage nodes 17.